1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacture, and more particularly, to an integrated circuit chip wherein different device widths of MOS transistors are obtained in the same circuit and on the same chip based on the depth of etch in a vertical direction.
2. Description of the Related Art
As very large scale integrated (VLSI) circuits become increasingly smaller, they eventually experience a physical limit set by the lithographic capability of their manufacture. In the past, 3-dimensional (3-D) transistor devices have been proposed to further shrink the packing density of integrated circuits. However, such techniques are very difficult to implement in any circuit other than an uniform array of memory cells. For example, in pitch-limited circuits, that is, the sense amplifier, row decoder, column decoder and other circuit elements needed for a memory integrated circuit can not be shrunk in the same manner as the individual memory cells. Therefore, the memory chip cell packing density can not be scaled down effectively. In implementing smaller cell sizes, such as six or seven times the minimum lithographic feature (6F or 7F square), there is not an overall DRAM chip area savings because the core or pitch limited circuits needed to access the memory cells can not be scaled proportionately when the pitch size is reduced.